1. Field of the Invention
The present invention relates to semiconductor design and manufacturing. More specifically, the present invention relates to a method and an apparatus for associating an error in a layout with a cell.
2. Related Art
As feature sizes on semiconductor chips continue to decrease at a dramatic rate, it is becoming progressively harder to deal with undesirable side effects that occur during various semiconductor manufacturing processes. To remedy this problem, designers often use a number of resolution enhancement techniques (RETs) to improve process performance.
Resolution enhancement techniques, such as optical proximity correction (OPC), typically transform the photomask by adding new sub-resolution patterns and/or by performing complex geometric manipulations to existing patterns. Unfortunately, even after applying such complex RETs, a photomask may still not be able to fully compensate for the undesirable side effects of semiconductor manufacturing processes. Hence, identifying and fixing errors in the layout by checking the design intent against its simulated silicon image is critically important.
Due to the relentless miniaturization of feature sizes, designers are being forced to use complex RETs on an ever increasing number of patterns. Unfortunately, present lithography verification techniques were not designed for such pervasive uses of complex RETs. Specifically, present verification techniques tend to report a large number of layout errors which are usually not summarized properly, which forces designers to spend a large amount of time identifying and fixing layout errors. This can increase time to market, which can result in millions of dollars in lost revenue.
Hence, what is needed is a method and an apparatus to help designers to quickly identify and fix errors in a layout.